Integrated ABB and DVS: A Post-silicon Tuning Approach for Parametric Yield Enhancement in Sub-45nm CMOS Technology

Abstract

Over the past decade, process parameter variations have been one of the key design challenges. At circuit level of abstraction, process parameter variations cause deviation in the design specifications which threaten the parametric yield, resulting cost implication on the semiconductor industry. Post-silicon tuning, such as Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) are the most commonly used techniques to mitigate the impacts of process parameter variations. However, since process parameter variations are getting aggravated with continued CMOS technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, we first examine the effect of process parameter variations on parametric yield loss. Further, we propose a framework that integrates ABB and DVS techniques to effectively mitigate the impacts of process parameter variations even for sub-45nm CMOS technology. We test the proposed approach w.r.t. Hybrid Redundant Multiply-and-Accumulate (HR-MAC) unit, however the proposed approach can be utilized for any digital circuit.