A Static-Reconfigurable Systolic Architecture using Barrel Shifters for High Speed Digital Signal Processing

Abstract

The throughput in high speed digital signal processing (DSP) applications is limited by both the processing speed of the processor employed for number-crunching operations and the capacity of the supporting communications link. Systolic arrays are special forms of multiprocessor architectures that partly overcome the memory band-width problem by allowing multiple computations for each memory access. In systolic arrays proposed so far, the computational element includes a multiplier and an accumulator. The multiplier in the basic cell requires either a large chip area if high speed is desired or becomes slower if serial architecture is used. A high speed programmable computational architecture without the multiplier is proposed in this paper. The new computational architecture is composed of basic cells consisting of a barrel-shifter and an accumulator. A throughput data rate which is inversely proportional to the delay in a single cell is achieved in the new architecture. The architecture is static reconfigurable to make use of the fact that the precision needed for coefficients in any filter or from one filter to another varies considerably. Hence the number of basic cells to implement multiplication by any coefficient is minimal and will depend upon the value of that coefficient only.