Towards Energy-Efficient Multi-Level Cell STT-MRAM Caches with Content Awareness

Abstract

Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is a promising memory technology, which has high density, low leakage power, fast read speed, and non-volatility, and is suitable for on-chip last-level caches with large capacity. Recently, Multi-Level Cell (MLC) STT-MRAM records two bits in a single cell to further improve the density for building even bigger on-chip caches. However, MLC worsens write energy consumption and endurance. The magnetization directions of its hard and soft domains cannot be flipped to two opposite directions simultaneously, which leads to the two-step transition problem for certain combinations of updating the 2-bit value. The two-step transition incurs extra flip in the soft domains, consume high energy, and negatively impact the life time of MLC STT-MRAM. In this paper, we present a new dimension to alleviate high write energy issue in MLC. During cache replacement, we select among a few candidates blocks close to the LRU position for replacement to lower the write energy with minimum impact on cache performance. We propose a novel block content encoding method to represent whole block with a few bits and use the encoding bits for better cache replacement. After picking the replacement block, we apply intelligent remap of each updated 2-bit values to further reduce the write energy. Performance evaluation results show this content-aware cache replacement can lower the write energy by 26.1% in comparison with MLC caches using regular Pseudo-LRU replacement polic