A 1.8GHz Digital PLL in 65nm CMOS

Abstract

A 1.8GHz high-accuracy, ring-oscillator based Digital Phase Lock Loop (DPLL), suitable for Serializer-Deserializer (SERDES) applications like HDMI, eSATA and USB2.0 is presented here. Sigma-Delta (??) dithering followed by passive filtering, along with Temperature Compensation is used to ensure frequency accuracy and low accumulated jitter, over a large temperature range. A re-circulating delay line based Time to Digital Converter (T2D) is used to handle large phase differences between the reference and feedback clocks. The DPLL is built in 65nm technology, and provides up to 1.8GHz output, with a phase noise of –87dBc/Hz at 1 MHz offset, and a frequency accuracy of +/-100ppm. It supports input frequencies in the range 0.7MHz to 50MHz, occupies a core area of 0.11 sq mm, and does not require external components.