Performance Comparison between SerDes and Time-Based Serial Links

Abstract

This paper presents a Performance comparison between the SerDes architecture and the time-based architectures. The challenges and the drawbacks in designing both architectures have been discussed. An example of 4-bit 2Gb/s and 5-bit 2.5Gb/s SerDes links and PPM-TDC links have been designed and simulated in 180nm CMOS technology. The FFT and the percentage energy concentrated in different bandwidths of the transmitted signals have been studied and compared. The timing diagram of the received signals at the end of 40-inch FR4 channel is provided and compared. 3Gb/s and 4Gb/s links have been designed and simulated too using SerDes and time-based approach and the results are compared. The time-based architectures show better performance over SerDes architectures when limited number of bits are transmitted