New CAD Tools to ConFigure Tree-Based Embedded FPGA

Abstract

An embedded FPGA (e-FPGA) is an IP which can be integrated in a System on Chip architecture to add more flexibility and reconfigurability to the design. This e-FPGA needs to be designed, optimized and configured differently compared to a classic FPGA chip. In this paper, we propose a full workflow to conFigure tree-based e-FPGA architecture. The workflow includes some existing tools used for mesh architecture. We modified these tools and adapt them accordingly to the proposed e-FPGA constraints. The new workflow reduces the execution runtime by an average of 57 % compared to the academic workflow used for mesh architecture. The e-FPGA area is also reduced by an average of 27% compared to the mesh architecture. This optimization is due to the ability of the CAD tools to manage the different processes of the configuration workflow for the tree-based architecture.