{"title":"Retargetable cache simulation using high level processor models","authors":"Rajiv A. Ravindran, R. Moona","doi":"10.1109/ACAC.2001.903371","DOIUrl":null,"url":null,"abstract":"During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simulator. The cache simulator has been implemented using a retargetable instruction set simulator from the Sim-nML processor description language. The retargetability helps in cache simulation and evaluation much before the actual processor design.","PeriodicalId":230403,"journal":{"name":"Proceedings 6th Australasian Computer Systems Architecture Conference. ACSAC 2001","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 6th Australasian Computer Systems Architecture Conference. ACSAC 2001","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACAC.2001.903371","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simulator. The cache simulator has been implemented using a retargetable instruction set simulator from the Sim-nML processor description language. The retargetability helps in cache simulation and evaluation much before the actual processor design.