C. Huyghebaert, Tom Schram, Q. Smets, T. K. Agarwal, D. Verreck, S. Brems, Alain Phommahaxay, D. Chiappe, S. E. Kazzi, C. L. D. L. Rosa, G. Arutchelvan, D. Cott, Jonathan Ludwig, A. Gaur, S. Sutar, A. Leonhardt, D. Marinov, D. Lin, M. Caymax, I. Asselberghs, G. Pourtois, I. Radu
{"title":"2D materials: roadmap to CMOS integration","authors":"C. Huyghebaert, Tom Schram, Q. Smets, T. K. Agarwal, D. Verreck, S. Brems, Alain Phommahaxay, D. Chiappe, S. E. Kazzi, C. L. D. L. Rosa, G. Arutchelvan, D. Cott, Jonathan Ludwig, A. Gaur, S. Sutar, A. Leonhardt, D. Marinov, D. Lin, M. Caymax, I. Asselberghs, G. Pourtois, I. Radu","doi":"10.1109/IEDM.2018.8614679","DOIUrl":null,"url":null,"abstract":"To keep Moore's law alive, 2D materials are considered as a replacement for Si in advanced nodes due to their atomic thickness, which offers superior performance at nm dimensions. In addition, 2D materials are natural candidates for monolithic integration which opens the door for density scaling along the 3rd dimension at reasonable cost. This paper highlights the obstacles and paths to a scaled 2D CMOS solution. The baseline requirements to challenge the advanced Si nodes are defined both with a physical compact model and TCAD analysis, which allows us to identify the most promising 2D material and device design. For different key challenges, possible integrated solutions are benchmarked and discussed. Finally we report on the learning from our first lab to fab vehicle designed to bridge the lab and IMEC's 300mm pilot line.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2018.8614679","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 45
Abstract
To keep Moore's law alive, 2D materials are considered as a replacement for Si in advanced nodes due to their atomic thickness, which offers superior performance at nm dimensions. In addition, 2D materials are natural candidates for monolithic integration which opens the door for density scaling along the 3rd dimension at reasonable cost. This paper highlights the obstacles and paths to a scaled 2D CMOS solution. The baseline requirements to challenge the advanced Si nodes are defined both with a physical compact model and TCAD analysis, which allows us to identify the most promising 2D material and device design. For different key challenges, possible integrated solutions are benchmarked and discussed. Finally we report on the learning from our first lab to fab vehicle designed to bridge the lab and IMEC's 300mm pilot line.
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