Exploring the viability of stochastic computing

Abstract

Recently, stochastic circuits have received significant attention from academia. Stochastic circuits claim to have a reduced energy consumption at the cost of accuracy and delay. In this paper, we explore the power, delay, energy and area of a stochastic circuit (a stochastic multiplier in particular), and compare these metrics with those of a regular multiplier, implemented using the Sum Of Products (SOP) approach. The SOP based multiplier is implemented both using a Kogge-Stone Adder, as well as a Ripple-Carry adder. Our results show that when the stochastic number generator (SNG) and counter are included in the stochastic multiplier (SM), even for 3 bits, the SM consumes more energy to finish one multiplication than an SOP based regular binary multiplier (RM), and this energy consumption grows exponentially as the number of bits increases. If we only consider the stochastic multiplier cell (SMC, which is simply a 2-input AND gate) and ignore the energy of the SNG and counter, the SMC has a better energy consumption for multiplications up to 12 bits. However, even for 3 bits, the SM (or the SMC) is slower by over 5x compared to the regular multiplier, and this delay increases exponentially as the number of bits increases. The area of the SM (including the area of the SNG and counter) is smaller for multipliers with more than 6 bits.