Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores

Abstract

The increase in Internet of Things $(\text{IoT})$ applications has triggered the development of energy-efficient embedded SoCs that can utilize limited energy sources. Relatively simple general-purpose processor cores are a vital component of SoCs, and op-timizing the power consumption, performance, and area is a key issue in the design of $\text{SoCs}$. Therefore, this study quantitatively compared the power, performance, and area of several 32-bit RISC-V cores with different microarchitectures. The simulation evaluations were performed for each processor with different pipeline configurations, with and without a multiplier and divider. The benchmark execution performance of the processors in a register transfer level (RTL) design, as well as the estimated power consumption and area based on logic synthesis and place-and-route using various CMOS process technologies are presented. Based on the results, we provided a brief guideline for the selection of microarchitectures for energy-efficient embedded SoCs.