{"title":"Interfacing Qubits via Cryo-CMOS Front Ends","authors":"A. Ruffino, Yatao Peng, E. Charbon","doi":"10.1109/CICTA.2018.8705712","DOIUrl":null,"url":null,"abstract":"This work describes a basic interface between solidstate quantum bits (qubits) and classical environments. We describe a multiplexer, a circulator, and a low noise amplifier, designed for cryogenic temperature operation in a 40 nm CMOS technology node. The circuits take advantage of traditional design styles, such as transmission gates, passive LC filters and switches, and recent developments, such as differential noise cancelling with six-port transformers, while exploiting new cryogenic CMOS (cryo-CMOS) modeling for design and verification purposes.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICTA.2018.8705712","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This work describes a basic interface between solidstate quantum bits (qubits) and classical environments. We describe a multiplexer, a circulator, and a low noise amplifier, designed for cryogenic temperature operation in a 40 nm CMOS technology node. The circuits take advantage of traditional design styles, such as transmission gates, passive LC filters and switches, and recent developments, such as differential noise cancelling with six-port transformers, while exploiting new cryogenic CMOS (cryo-CMOS) modeling for design and verification purposes.