The Intel® Many Integrated Core Architecture

A. Duran, Michael Klemm
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引用次数: 120

Abstract

In recent years, an observable trend in High Performance Computing (HPC) architectures has been the inclusion of accelerators, such as GPUs and field programmable arrays (FPGAs), to improve the performance of scientific applications. To rise to this challenge Intel announced the Intel® Many Integrated Core Architecture (Intel® MIC Architecture). In contrast with other accelerated platforms, the Intel MIC Architecture is a general purpose, manycore coprocessor that improves the programmability of such devices by supporting the well-known shared-memory execution model that is the base of most nodes in HPC machines. In this presentation, we will introduce key properties of the Intel MIC Architecture and we will also cover programming models for parallelization and vectorization of applications targeting this architecture.
Intel®多集成核心架构
近年来,高性能计算(HPC)架构的一个明显趋势是包含加速器,如gpu和现场可编程阵列(fpga),以提高科学应用的性能。为了应对这一挑战,英特尔宣布了英特尔®多集成核心架构(英特尔®MIC架构)。与其他加速平台相比,英特尔MIC架构是一种通用的多核协处理器,它通过支持众所周知的共享内存执行模型(HPC机器中大多数节点的基础)来提高这些设备的可编程性。在本演讲中,我们将介绍英特尔MIC架构的关键特性,并将介绍针对该架构的应用程序的并行化和向量化编程模型。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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