Fractional frequency synthesizer using flying adder principle

Abstract

The frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, phase locked loop fractional architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency. Flying-Adder architecture is an emerging technique which is based on a new concept time-average-frequency, to generate frequencies. This paper presents simple fractional frequency synthesizer architecture based on concept flying-adder and phase locked loop principle. The simulation results concerning this approach are presented.