An 8kbit RAM + I/O Peripheral Circuit for Microprocessors

ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI:10.1109/ESSCIRC.1980.5468790

K. Horninger, G. Grassl, I. Bromme, U. Schwabe

引用次数: 0

Abstract

An 8 kbit RAM + I/O peripheral circuit for microprocessors has been realized in a scaled NMOS single-layer poly technology. Cycle time is 250 ns, counter frequency is 10 MHz, chip size is 27.6 mm2 and the supply current is approx. 200 mA, with 5 V supply voltage.

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用于微处理器的8kbit RAM + I/O外围电路

采用规模化的NMOS单层多晶技术，实现了8kbit RAM + I/O微处理器外围电路。周期时间为250ns，计数器频率为10mhz，芯片尺寸为27.6 mm2，电源电流约为。200ma, 5v供电电压。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

ESSCIRC 80: 6th European Solid State Circuits Conference

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