Compact circuit simulation model of silicon carbide static induction and junction field effect transistors

Abstract

The electrical characterization and model development for silicon carbide (SiC) vertical channel SIT and JFET structures are presented in this work. A compact model is developed based on the device geometry and SiC material properties. The model is validated against measured data at 25/spl deg/C and 100/spl deg/C for a prototype 0.03 cm/sup 2/ SiC SIT provided by Northrop Grumman. Validation is also done against the power JFET present in the combined MOSFET-SiC JFET cascode structure from SiCED. The model's on-state and transient characteristics are validated over this temperature range. Validation of the model shows excellent agreement with measured data. The physics-based approach implemented in this model is crucial to describing the transient behavior over a wide range of application conditions and temperature ranges.