{"title":"Increasing breakdown voltage of p-channel LDMOS in BCD technology with novel backside process","authors":"C. Schmidt, G. Spitzlsperger","doi":"10.23919/ISPSD.2017.7988958","DOIUrl":null,"url":null,"abstract":"A novel concept for a BCD technology is presented which comprises the processing of the wafer on the thinned backside and which offers — similar to SOI technology — a full dielectric isolation of power devices. Limitations of the breakdown voltage of p-LDMOS encountered in conventional BCD technologies are overcome by replacing the commonly applied deep n well layer by an n+ region formed on the wafer backside and by connecting the n+ region with a TSV to the source potential on the front side. The fabricated p-LDMOS with drift length 5.7μm has a breakdown voltage (BVdss) of −115 V and an on-resistance (Ron) of 320 mΩ mm. It is found by TCAD simulations that further optimization of the p-LDMOS with respect to BVdss, Ron and electrical SOA can be achieved by adding an n-type RESURF layer below STI.","PeriodicalId":202561,"journal":{"name":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/ISPSD.2017.7988958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A novel concept for a BCD technology is presented which comprises the processing of the wafer on the thinned backside and which offers — similar to SOI technology — a full dielectric isolation of power devices. Limitations of the breakdown voltage of p-LDMOS encountered in conventional BCD technologies are overcome by replacing the commonly applied deep n well layer by an n+ region formed on the wafer backside and by connecting the n+ region with a TSV to the source potential on the front side. The fabricated p-LDMOS with drift length 5.7μm has a breakdown voltage (BVdss) of −115 V and an on-resistance (Ron) of 320 mΩ mm. It is found by TCAD simulations that further optimization of the p-LDMOS with respect to BVdss, Ron and electrical SOA can be achieved by adding an n-type RESURF layer below STI.