A hardware accelerator board for cellular neural networks: CNN-HAC

IEEE International Workshop on Cellular Neural Networks and their Applications Pub Date : 1990-12-16 DOI:10.1109/CNNA.1990.207520

T. Roska, G. Bártfai, P. Szolgay, T. Szirányi, A. Radványi, T. Kozek, Z. Ugray

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引用次数: 24

Abstract

The hardware accelerator (HAC) boards using catalog programmable VLSI ICs represent a trade-off having higher reconfigurability and lower cost. This paper presents such a solution for a cellular neural network (CNN). The architecture of the present design (CNN-HAC) using 4 standard DSPs to calculate the transient response of a one-layer CNN containing 0.25-1.0 million analog neural cells is presented. The architecture and also the design principles are independent of the number of processors. The actual design was made in the form of a PC add-on board. The global control unit, which connects the board to the host firmware and communicates control signals to/from the local control units of the DSPs, was realized mainly with EPLDs. A special correspondence between the virtual processing elements-calculating the time discrete models of the analog neural cells-and the physical ones, established to work an architecture with an infrequent, one-directional interprocessor communication, is discussed in detail.<>

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用于细胞神经网络的硬件加速板:CNN-HAC

使用目录可编程VLSI集成电路的硬件加速器(HAC)板代表了具有更高可重构性和更低成本的权衡。本文针对细胞神经网络(CNN)提出了这样一种解决方案。本设计(CNN- hac)使用4个标准dsp来计算包含25- 100万个模拟神经细胞的单层CNN的瞬态响应。架构和设计原则与处理器的数量无关。实际的设计是以PC附加板的形式进行的。全局控制单元主要通过epld实现，它将主控板与主机固件连接起来，并与dsp的本地控制单元进行控制信号的通信。详细讨论了虚拟处理单元(计算模拟神经细胞的时间离散模型)与物理处理单元之间的特殊对应关系，这种对应关系建立在一个具有不频繁的单向处理器间通信的架构中

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE International Workshop on Cellular Neural Networks and their Applications

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