Full Adder Cell for Low Power Arithmetic Applications

Abstract

Arithmetic circuits like adder, multiplexer etc. arethe most important circuits in digital signal processing andmany more applications. Full adder circuit is the basic cell ofarithmetic circuits. Many applications require circuits of highthroughput, small area and consume ultra-low power. In thisregards, this paper brings forward a new full adder circuitthat uses 10-Transistors and improved version of the proposed circuit. This full adder uses low power XOR gates to generate sum signal and a multiplexer of two transistors, to generate carry out signal. Generic Process Design Kit (GPDK) 45nm technology is employed in Cadence virtuoso design environment to design circuits which are simulated with Spectre simulator.