Impact of Clustering Algorithms on the performance of Multilevel Switch Boxes FPGA with Long Wires

Abstract

Computer-Aided Design (CAD) tools represent a major factor to enhance the quality of Field Programmable Gate Arrays (FPGAs) and use their architectural resources to their full potential. Since they can be developed to satisfy application constraints like surface, speed and energy while responding to Time-to-market requirements. In this paper, we explore the impact of T-VPack and First Choice (FC) clustering algorithms on the performance of Multilevel Switch Boxes (MS) FPGA with Long Wires (LWs). Indeed, the performance of an FPGA is highly sensitive to the mapping of Logic Blocks (LBs) on FPGA architecture. This work shows that FC ameliorates power consumption, area, critical path delay and energy compared to T-VPack.