SoC Design of a Dual-Mode Transceiver for Power-Line Telecommunications

Abstract

In this paper, the design of a dual-mode transceiver for a power-line telecommunications (D-PLT) is described. We investigate on designing a system architecture of the D-PLT, adopting an efficient modulation technique against power-line channel and supporting a high reliability, which is well suited for the CENELEC B, C, and D bands roughly from 90 to 150 kHz. The proposed D-PLT is eventually integrated to a system-on-a-chip (SoC), synthesizing all of a baseband transceiver, a channel forward error correction (FEC) module, a micro-controller unit (MCU) to access communication protocols, and analog front end circuits, i.e., a pre-amplifier, a gain-amplifier, a digital-to-analog converter (DAC), a comparator, as well as external interfaces to communicate with application layer. The designed D-PLT is fabricated utilizing a mixed 0.18 um CMOS technology and it is required a total area of about 9,576 mm^2 consuming about 148 mW at the maximum data rates of 2.5 kbps.