A novel low-power and high-performance dual-loop DLL with linear delay element

Abstract

This paper describes a dual-loop DLL architecture with linear delay element in analog loop and a monotonic digitally controlled delay element in its digital loop. The proposed architecture is based on two loops, fine loop and coarse loop which is controlled by peripheral circuits such as FSM (finite state machine) and lock detector circuit. The ADS simulator is used to verify the circuit design. All of simulations are based upon 0.18 mum CMOS technology at 1.8 V power supply voltage. The simulation results show that the proposed DLL has wide-range operation from 200 to 400 MHz and low-power dissipation and low-jitter performance. Moreover, the rms jitter is as low as 20 ps and the power dissipation is as low as 4.5 mW over the operating frequency range.