{"title":"Software testing of a simple network","authors":"Jack H. Arabian","doi":"10.1109/EWDTS.2011.6116429","DOIUrl":null,"url":null,"abstract":"It is costly to have defective networks and nodes. There are many factors involved in the cost of defective design of networks. The size of development team, stage of development when the defect occurs, routing protocols and subtlety of the defect are only a few of the possibilities. Testing software, therefore has to be designed to detect the defect, and as early as possible in the design cycle. Otherwise the costs can be overwhelming. This is yet another compelling argument for QA engineers to justify up-front test costs similar to the electronics design programs of JTAG (Joint Test Action Group for boundary scan) or BIST (Built-in Self Test) circuitry.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 9th East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2011.6116429","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
It is costly to have defective networks and nodes. There are many factors involved in the cost of defective design of networks. The size of development team, stage of development when the defect occurs, routing protocols and subtlety of the defect are only a few of the possibilities. Testing software, therefore has to be designed to detect the defect, and as early as possible in the design cycle. Otherwise the costs can be overwhelming. This is yet another compelling argument for QA engineers to justify up-front test costs similar to the electronics design programs of JTAG (Joint Test Action Group for boundary scan) or BIST (Built-in Self Test) circuitry.