Optimization design of under voltage lockout circuit in power management chips based on standard BCD process

Abstract

An optimization design of an Under Voltage Lockout (UVLO) circuit in a bipolar CMOS DMOS (BCD) process is presented in this paper. Compared with the traditional structure, the proposed circuit effectively reduces the hysteresis voltage drift with temperature by introducing the high-order temperature compensation function to the band-gap reference. Thus, the reliability of the UVLO circuit is improved. The designed UVLO circuit has an input high threshold voltage of 8.2 V, low threshold voltage of 5.6 V and a hysteresis range of 2.6 V when T = 25C. The maximum deviation is 0.3V within −30 ∼ 140C. In a standard BCD process, the designed circuit is simulated by using Spectre in Cadence. The feasibility and correctness of the designed UVLO circuit is proven by the simulation results.