A 500-MS/s 8-b Low Power High Speed Asynchronous SAR ADC in 40-nm CMOS

Abstract

This paper presents a 500-MS/s 8-b single-channel asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that achieves low input frequency SNDR/SFDR of 45.89/58.9 dB, while the SNDR/SFDR near Nyquist is 44.75/58.8 dB with excellent power efficiency. The ADC adopts background digital detection with analog calibration techniques to correct offset mismatch. The high linearity is guaranteed by a kind of fast input bootstrapped circuits as the input switches. Furthermore, the proposed double-tail dynamic comparator and Set-and-Down structure capacitive digital-to-analog converter (CDAC) save the overall energy. The total power consumption is 0.61mW under a 1.1-V supply.