{"title":"Compact Design of 60-GHz Wilkinson Power Dividers in a 65-nm CMOS Process for Monolithic Microwave Integrated Circuits","authors":"Hongyu Bao, S. Lam","doi":"10.1109/ICEIC57457.2023.10049935","DOIUrl":null,"url":null,"abstract":"This paper reports miniature designs of 60-GHz Wilkinson power dividers based on a multi-metallization transmission line structure for monolithic microwave integrated circuits (MMICs). In a 65-nm 2P8M CMOS process, a straight elongated design occupies an area of 56 × 610 μm2, giving an insertion loss lower than 0.89 dB, a return loss better than 30 dB and an isolation higher than 45 dB at 60 GHz. The meandered design further reduces the chip area to 68 × 310 μm2 (≈ 0.021 mm2) and it also provides a low power loss and a high isolation in a frequency range over 20 GHz. The compact designs are extendable to other deep sub-micron CMOS processes for development of MMICs.","PeriodicalId":373752,"journal":{"name":"2023 International Conference on Electronics, Information, and Communication (ICEIC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 International Conference on Electronics, Information, and Communication (ICEIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEIC57457.2023.10049935","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper reports miniature designs of 60-GHz Wilkinson power dividers based on a multi-metallization transmission line structure for monolithic microwave integrated circuits (MMICs). In a 65-nm 2P8M CMOS process, a straight elongated design occupies an area of 56 × 610 μm2, giving an insertion loss lower than 0.89 dB, a return loss better than 30 dB and an isolation higher than 45 dB at 60 GHz. The meandered design further reduces the chip area to 68 × 310 μm2 (≈ 0.021 mm2) and it also provides a low power loss and a high isolation in a frequency range over 20 GHz. The compact designs are extendable to other deep sub-micron CMOS processes for development of MMICs.