The design and simulation of a 400/533Mbps DDR-II SDRAM memory interconnect bus

Abstract

A major bottleneck in todaypsilas computer system performance is the speed of the main memory bus. A memory bus should be carefully designed for good signal integrity (SI) and timing performance. This paper presents the design, modelling and simulation of a double data rate synchronous dynamic RAM (DDR-II SDRAM) memory bus operating at 400/533 Mbps. Three bus topologies are investigated and compared in terms of the amount of inter-symbol-interference (ISI) and the eye-width (EW). The topology with on-die-termination (ODT) gave about 95% improvement in ISI reduction, and about 37% and 12% improvement in the eye-width for the worst case write and read operations for the 400 Mbps data rate, respectively, when compared to the conventional mother board termination (MBT) scheme.