Modeling and suppression of the surface trap effect on drain current frequency dispersions in GaAs MESFETs

Abstract

Drain current frequency dispersions (gate-lag) in GaAs MESFETs have been investigated and a novel surface trap model is proposed which reveals the mechanism of gate-lag. Assuming two kinds of surface traps with a delay time of 28 msec and 5 msec, the fitting curve agrees with the measured drain current transients. The dependence of gate-lag on various operating bias conditions such as pulse period, applied pulse voltage, and drain bias has been also observed. Furthermore, it is confirmed that the double recessed structure with the inner recess depth of 500 /spl Aring/ is available for the reduction of gate-lag.