FPGA Implementation of a Power-Efficient and Low-Memory Capacity Turbo Decoding Architecture

Abstract

In this demo, we introduce and implement a power efficient and low-memory capacity Turbo decoding architecture for LTE-Advanced standard on field programmable gate array (FPGA). In addition, the performance comparison and power estimation are presented. As compared with the traditional decoding architecture, the memory capacity is reduced by 67.4%, and the decoding performance is acceptable in practice. Moreover, the overall power consumption is decreased by 34.6% at the frequency of 100MHz.