8-Channels high-resolution TDC in FPGA

Abstract

In this contribution we presented the implementation of a tapped-delay-line (TDL) TDC with 8-channels in a Xilinx Kintex-7 FPGA device with r.m.s. value of the resolution around 20 ps. Main features of the instrument are the resource-saving and low-power architecture, the presence of an edge detector able to sense the position of the transition propagating along the delay line within one clock cycle, the interface through a USB 3.0 communication gate.