Low noise rail-to-rail amplifier runs fast at ultra low currents and targets energy harvesting

Ali Far
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引用次数: 4

Abstract

An input-output rail-to-rail buffer amplifier is presented that is low noise, fast, and operates at ultra low currents. The amplifier targets energy harvesting applications that require low cost, high volume, and rugged manufacturing by avoiding use of non-standard device configurations or special processes. The main contributions of this work are: (1) The method of lowering voltage output noise by narrow-banding an amplifier, while introducing a time dependent bias current boost that is triggered by large differential input signals. Narrowbanding an amplifier to reduce its output noise, slows its dynamic response, and this method aims to restore and boost both the amplifier's slew rate and settling time. (2) Amplifier can operate at low VDD of about VGS+2VDS, while running in subthreshold, based in standard 0.18u digital CMOS. (3) PMOSFETs are utilized as inputs, compensation capacitors, and bias resistors in both the amplifier and the boost stages, which helps optimize for yield and lower noise. More importantly, the dynamic response of both the main amplifier and the boost stage being substantially dependent on PMOSFET device parameters, facilitates a smoother dynamic response in and out of boost, over process and operating variations. Based on montecarlo (MC) and worst case (WC) simulations, the following specifications are achievable: voltage output noise (VOnOiSe) of 10 uv/Hz⁁1/2 at 1KHz, supply current (Idd) ∼ 500 nA; Vdd minimum ∼0.6V; rail-to-rail voltage input (VIN) range and output voltage (VOUT) range of ∼ +/− 25mv from the rails; output resistor load (Rl) ∼2k Ohms; output capacitor load (Cl) ∼1nF; slew-rate (SR) −/+ ∼ 4/2.5 v/us; settling time (tS) ∼ 5us to 1%; power supply rejection ratio (PSRR) −/+ ∼ 80dB/85dB, common mode rejection ration (CMRR) ∼ 125dB, unity gain bandwidth (fr) ∼ 20KHz with phase margin (PM) ∼ 75 degrees; open loop gain (G) ∼ 85dB; preliminary area estimate of ∼ 180 um per side.
低噪声轨对轨放大器在超低电流下快速运行,目标是能量收集
提出了一种低噪声、快速、超低电流的输入输出轨对轨缓冲放大器。该放大器的目标是能量收集应用,需要低成本,高容量和坚固耐用的制造,避免使用非标准设备配置或特殊工艺。这项工作的主要贡献是:(1)通过窄带放大器降低电压输出噪声的方法,同时引入由大差分输入信号触发的时间相关偏置电流升压。窄带可以降低放大器的输出噪声,降低其动态响应速度,这种方法旨在恢复和提高放大器的摆幅率和稳定时间。(2)基于标准的0.18u数字CMOS,放大器可以在VGS+2VDS左右的低VDD下工作,同时在亚阈值下运行。(3) pmosfet用作放大器和升压级的输入、补偿电容器和偏置电阻,这有助于优化良率和降低噪声。更重要的是,主放大器和升压级的动态响应在很大程度上取决于PMOSFET器件参数,这有助于在升压、过程和操作变化中实现更平滑的动态响应。基于蒙特卡罗(MC)和最坏情况(WC)模拟,可以实现以下规格:电压输出噪声(VOnOiSe)在1KHz时为10 uv/Hz 1/2,电源电流(Idd) ~ 500 nA;Vdd最小~ 0.6V;轨对轨电压输入(VIN)范围和输出电压(VOUT)范围为~ +/−25mv;输出电阻负载(Rl) ~ 2k欧姆;输出电容负载(Cl) ~ 1nF;自旋速率(SR)−/+ ~ 4/2.5 v/us;沉降时间(tS) ~ 5us ~ 1%;电源抑制比(PSRR)−/+ ~ 80dB/85dB,共模抑制比(CMRR) ~ 125dB,单位增益带宽(fr) ~ 20KHz,相位裕度(PM) ~ 75度;开环增益(G) ~ 85dB;每边的初步面积估计为~ 180 um。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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