Xiaojie Zhang, Maodong Wang, Liyang Guo, Xinghua Wang
{"title":"A 12-bit 200KS/s SAR ADC with digital self-calibration","authors":"Xiaojie Zhang, Maodong Wang, Liyang Guo, Xinghua Wang","doi":"10.1109/IAEAC.2017.8054480","DOIUrl":null,"url":null,"abstract":"Aiming at the application of neural signal detection system, this paper designs a 12-bit 200KS/s high resolution successive approximation analog-to-digital converter (SAR ADC) fabricated in SMIC 0.18-μm process. An optimized digital self-calibration technique is proposed to correct the static offset of the comparator and the mismatch of the capacitor array by using a correction capacitor array, achieving 1-bit improvement of ENOB. Simulation results show that, when the input signal is 46K, the ADC fulfills an SNDR of 71.55dB and an SFDR of 91.82dB with a 200KS/s sampling rate, while the ADC only can achieve an SNDR of 65.85dB and an SFDR of 78.83dB before calibration. With the ENOB of 11.59 bit, the self-calibration SAR ADC consumes 336μW at 1.8 V power supply.","PeriodicalId":432109,"journal":{"name":"2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IAEAC.2017.8054480","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Aiming at the application of neural signal detection system, this paper designs a 12-bit 200KS/s high resolution successive approximation analog-to-digital converter (SAR ADC) fabricated in SMIC 0.18-μm process. An optimized digital self-calibration technique is proposed to correct the static offset of the comparator and the mismatch of the capacitor array by using a correction capacitor array, achieving 1-bit improvement of ENOB. Simulation results show that, when the input signal is 46K, the ADC fulfills an SNDR of 71.55dB and an SFDR of 91.82dB with a 200KS/s sampling rate, while the ADC only can achieve an SNDR of 65.85dB and an SFDR of 78.83dB before calibration. With the ENOB of 11.59 bit, the self-calibration SAR ADC consumes 336μW at 1.8 V power supply.