Early-Stage Timing Prediction in SoC Physical Design using Machine Learning

Abstract

During the late CMOS period, companies that manufacture semiconductors and electronics are subject to extreme product schedule tension notwithstanding different types of competitive strain. Inside this system, electronic plan automation (EDA) is expected to convey “plan based comparable scaling” to help with keeping up with crucial industry trajectories. The execution of machine learning techniques “inside” as well as “around” plan devices and work processes will act as a powerful main thrust in such manner. The valuable open doors for machine learning are discussed in this paper, with a particular accentuation on the physical execution of ICs. Instances of applications include eliminating unnecessary plan and demonstrating edges through correlation mechanisms, accomplishing quicker plan convergence through predictors of downstream stream outcomes that comprehend the two instruments and configuration instances, and (3) corollaries such as enhancing the utilization of plan resources licenses and accessible schedules. The limits of machine learning in coordinated circuit physical plan are discussed in the last section of the paper.