{"title":"Texas Instruments' 4 Mb DRAM-a new, faster generation of DRAM","authors":"C.W. Rhodine","doi":"10.1109/NAECON.1991.165766","DOIUrl":null,"url":null,"abstract":"A 4-Mb DRAM (dynamic random access memory) family which improves upon the performance of the 1 Mb DRAM family is described. While increasing storage density and reducing memory access times, overall chip size is minimally affected. Development of 0.9- mu m CMOS technology for use on the 4-Mb DRAM allowed immediate speed and size improvements over the 1-Mb DRAM. Continual review of lessons learned on previous design insures that each successive DRAM generation is both more efficient in terms of architecture and more reliable in system use. In the case of the 4-Mb DRAM, this dedication to improvement has resulted tin a 20% speed enhancement, moderate size increase (1.6X), and improved reliability results.<<ETX>>","PeriodicalId":247766,"journal":{"name":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 1991 National Aerospace and Electronics Conference NAECON 1991","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.1991.165766","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 4-Mb DRAM (dynamic random access memory) family which improves upon the performance of the 1 Mb DRAM family is described. While increasing storage density and reducing memory access times, overall chip size is minimally affected. Development of 0.9- mu m CMOS technology for use on the 4-Mb DRAM allowed immediate speed and size improvements over the 1-Mb DRAM. Continual review of lessons learned on previous design insures that each successive DRAM generation is both more efficient in terms of architecture and more reliable in system use. In the case of the 4-Mb DRAM, this dedication to improvement has resulted tin a 20% speed enhancement, moderate size increase (1.6X), and improved reliability results.<>