A 0.5V True-Single-Phase 16T Flip-Flop in 180-nm CMOS for IoT Applications

Abstract

A low voltage and low power true-single-phase flip-flop (FF) design using 16-transistor only is proposed. It is adapted from conventional master-slave based design and reduces layout area by using hybrid logic scheme. Optimization measures have resulted in a new FF with better power and area performances. Based on simulation results using the TSMC CMOS 180nm, our design achieves the conventional TGFF design by 67.3% in energy and 30.8% in layout area.