Novel symmetric high Q inductors fabricated using wafer-level CSP technology

Abstract

Wafer level chip-size package (WLP) technology enables fabrications of low-loss high-Q inductors, which suffer from unfavorable two-port asymmetric characteristics. To overcome this problem, a novel clip-type inductor has been proposed, where the electrode crossover points in multi-turn inductor structures is modified from a conventional mirror symmetric point to a novel electrical symmetric point. The novel clip inductors were designed and fabricated using WPL technology. By means of a developed 4-nH novel clip inductor, the Q-factor value difference between the two ports can be significantly reduced to 1.4% from 14.8% at 1.4 GHz. Q-factors of developed inductors have also been evaluated under both a conventional short-circuited load condition and an impedance matched condition.