The ARISE Reconfigurable Instruction Set Extensions Framework

2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation Pub Date : 2007-07-16 DOI:10.1109/ICSAMOS.2007.4285746

N. Vassiliadis, G. Theodoridis, S. Nikolaidis

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引用次数: 5

Abstract

In this paper, we introduce the ARISE framework for the systematic extension of typical processors with the necessary infrastructure to support arbitrary number and type of reconfigurable hardware units. ARISE extends the micro-architecture of the processor with an interface to allow the coupling of the hardware units. Furthermore, the instruction set of the processor is extended with instructions which expose to the programmer/compiler the full control of the interface. This control includes the configuration of operations on the hardware units, execution of these operations, and communication of data between the processor and the units. The new instructions are incorporated without the need to redesign the processor instruction set architecture. To evaluate our proposal a model of an ARISE extended MIPS processor has been designed. Using a turbodecoder algorithm as benchmarking application a simulation of the ARISE model has been performed. Performance results show impressive application speedups up to times7.5.

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ARISE可重构指令集扩展框架

在本文中，我们介绍了用于系统扩展典型处理器的ARISE框架，该框架具有必要的基础设施，以支持任意数量和类型的可重构硬件单元。ARISE扩展了处理器的微体系结构，提供了一个接口，允许硬件单元的耦合。此外，处理器的指令集扩展了一些指令，这些指令向程序员/编译器公开了对接口的完全控制。这种控制包括硬件单元上的操作配置、这些操作的执行以及处理器和单元之间的数据通信。合并新指令无需重新设计处理器指令集体系结构。为了评估我们的建议，我们设计了一个扩展MIPS处理器的模型。采用涡轮解码器算法作为基准应用，对ARISE模型进行了仿真。性能结果显示令人印象深刻的应用程序加速高达7.5倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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