Comparing Different PC and FPGA Implementation Possibilities of Fast Multipole Method

Abstract

In this paper our aim is to compare the efficiency of different hardware platforms during the solution of the Fast Multipole Method (FMM). The brute force solution has also been compared to the highly topographical FMM algorithm to reflect the advantages and disadvantages of the concept. During the implementation we attempted to benefit from the different properties of the hardware platforms (e.g.: multi computation cores in PCs and array clusters in Field Programmable Gate Arrays - FPGAs). We demonstrate different implementations on PC and on FPGA with high-level hardware synthesis and benchmark the resulting hardware in terms of speed, and power consumption.