Xi Zhang, Dongsheng Wang, Y. Xue, Haixia Wang, Jinglei Wang
{"title":"A Novel Cache Organization for Tiled Chip Multiprocessor","authors":"Xi Zhang, Dongsheng Wang, Y. Xue, Haixia Wang, Jinglei Wang","doi":"10.1007/978-3-642-03644-6_4","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":243555,"journal":{"name":"Advanced Parallel Programming Technologies","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Advanced Parallel Programming Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-3-642-03644-6_4","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1