MultiChipSat Fault-Tolerant Architecture

Abstract

With the process size of microelectronics shrinking well below 90 nm, the characteristics of upsets experienced by spacecraft avionics are drastically changing; traditional hardware mitigation techniques are reaching performance limitations. A method for achieving reliability, along with the performance capabilities of new technologies, is through the use of an innovative avionics architecture which utilizes both software and hardware redundancy techniques to achieve reliability. Instead of ensuring consistent reliability levels to every operation, the fault mitigation levels are user defined for each operation. Thus the architecture allows the system to be optimized about the needed fault tolerance and performance characteristics of each operation through its use of tightly coupled hardware and software design.