Queuing Theory-Guided Performance Evaluation for a Reconfigurable High-Speed Device Interconnected Bus

Abstract

UM-BUS, a reconfigurable high-speed device- interconnected bus, also characteristic of dynamic fault-tolerance and remote access has been proposed to enablelightweight sensor system design in IoTs. Performanceprediction is a key step to build an idea of the worst or best casesbefore real-world deployment of UM-BUS-based systems. Thispaper proposes a queuing theory-guided analytic model whichallows us to obtain an approximation for the average packetdelay as well as exact upper and lower bounds. A set ofexperiments based on MATLAB simulation are conducted to doperformance evaluation. Finally design insights are given forpragmatic implementation.