Serial acquisition of PN sequences in chip-asynchronous DS/SS systems

Abstract

The problem is to obtain an estimate of the unknown delay /spl delta/=(k+/spl epsiv/)T/sub c/, where k is an integer, /spl epsiv//spl isin/[0,1], and T/sub c/ is the chip time duration. This paper concentrates on the estimation of k using sequential probability ratio tests (SPRTs), details on the estimation of /spl epsi/ being published separately. It assumes a random sequence model for the PN sequences arising in the out-of-phase hypothesis, and derives an SPRT which does not depend on /spl epsi/. The error probabilities and expected sample sizes are compared with those obtained in both ideal case where the SPRT depends on /spl epsi/, and in the case where the SPRT is based on a zero sequence model for the out-of-phase hypothesis. These comparisons are made in both of the situations where the observations are random sequences, or actual PN sequences as would be used in practice. The analytical and numerical results indicate that the SPRT based on the random sequence model yields excellent performance independent of the unknown value of /spl epsi/, and significantly outperforms the SPRT based on the zero sequence model.<>