Electron induced SEU and MBU sensitivity of 20-nm planar and 16-nm FinFET SRAM-based FPGA

Abstract

The electron induced SEU risk on Earth missions is usually considered as negligible, though previous works have demonstrated that electrons could trigger SEU in CMOS devices. In fact, the high energy electron fluxes are too low in Earth space environment to represent a real threat, from the SEE point of view, in currently used device technologies for space applications. Nevertheless, the increasing use of highly integrated CMOS technologies raises the question of the SEU electron sensitivity in the most recent technology nodes. Moreover, if the SEU sensitivity becomes significant in sub-28-nm devices, the system reliability may also be affected by the MBU risk. This work investigates about the electron induced SEU sensitivity of recent CMOS technologies. The related question of the MBU risk due to electrons in space environment is also studied. The devices exposed to electron beams are SRAM-based Xilinx FPGA manufactured in 20-nm planar and 16-nm FinFET technologies. Detailed 3D device circuit models were done with TRADCARE®. This tool was also used as interface to GEANT4 for forward Monte-Carlo simulations. An SRAM cell electrical layout was also implemented in TRADCARE to consider the electrical behaviour of the circuit. The TRADCARE/GEANT4 calculation outputs were used to explain and discuss the experimental sensitivities observed under 18 MeV electron beam.