Position-aware thread-level speculative parallelization for large-scale chip-multiprocessor

Abstract

Thread-Level Speculation (TLS) is an effective mechanism for exploiting automatic parallelization of the sequential programs, especially for the large scale chip multiprocessor (CMP) which is rich of idle computation resources on chip. TLS could use the idle computation resources to improve the performance of sequential program. However, the inter-thread correlation between the speculative threads requests more careful core assignment and thread scheduling for the TLS execution, rather than the conventional threads. Analysis shows that there is a high correlation between TLS execution performance and the on-chip "position" of the cores assigned for the TLS execution. Accordingly, we propose a "position-aware" task scheduling strategy for the thread-level speculative parallelization. We introduce a model to evaluate the "Centre of Data Gravity (CDG)" of the TLS program, and propose a new core assignment and thread scheduling mechanism based on CDG for the TLS execution. Tests show that, these strategies have achieved significant performance improvement: compared with the original TLS that does not consider the factor, the range of performance improvement is from 4.6% to 39%.