A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only)

Abstract

The programmability of an FPGA poses a number of challenges when it comes to complete and comprehensive testing of the FPGA itself. A large number of configurations must be downloaded into the FPGA to test the programmable sources. A great many methods were proposed to reduce the number of configurations to minimize the test time, but few of papers were focus on reducing single configuration time. This paper proposes a novel method to reduce more than 30% of the total configuration time based on partial reconfiguration technology and sorting algorithm. This method is implemented on a series of SRAM-based FPGAs. The experimental result shows that this method reduces 30%-45% of the total configuration time and can be generally applied to all SRAM-based FPGAs currently.