A net-based semantics for VHDL

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410685

W. Damm, B. Josko, R. Schlör

引用次数: 24

Abstract

The VHDL standard gives only an informal description of the semantics of VHDL. To apply formal verification techniques, a precise semantics definition is necessary. A formal semantics for VHDL based on interpreted Petri nets is defined. The presented semantics is compositional and provides a link to automatic verification methods for VHDL based designs.<>

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一个基于网络的VHDL语义

VHDL标准只给出了VHDL语义的非正式描述。为了应用正式的验证技术，精确的语义定义是必要的。定义了基于解释Petri网的VHDL的形式化语义。所提出的语义是组合的，并为基于VHDL的设计提供了自动验证方法的链接。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

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