Dynamic Circuit Model of SiC VJFET For Power Integrated Circuit Design

Abstract

This paper presents a novel dynamic model of the vertical SiC JFET with a lateral channel for power-integrated-circuit design. The terminal capacitances of the normally-on SiC JFET device present a critical influence on switching waveforms and switching losses for dynamic models. This fundamental parameter is firstly taking into account in our suggested approach. The proposed capacitance model is based on a comparison between C-V measurements and numerical TCAD simulations and implemented in the VHDL-AMS hardware description language. The effectiveness of our approach is proved with experimental results under inductive-resistive switching conditions and under capacitance--voltage measurements.