From behavioral to RTL models: an approach

Abstract

Presents an approach for developing register transfer level (RTL) system models from behavioral models. Synchronous data flow principals are used to assist the transition. Our approach is based on a model of synchronous VLSI components which describes both their behavior, and their timing diagrams at a register transfer level. The component model permits the verification of correct synchronization at a system level. Initialization and termination conditions are explicitly checked.<>