{"title":"Simulation study and comparative analysis of proposed novel hybrid DG-TFET with conventional TFETs structures for improved performance","authors":"Aadil Anam, S. Amin, D. Prasad","doi":"10.1109/iSES52644.2021.00079","DOIUrl":null,"url":null,"abstract":"In this paper, the simulation study and comparative analysis of the proposed novel hybrid Double-Gate Tunnel Field Effect Transistor (DG-TFET) are extensively done with different conventional TFET structures (different semiconductor materials like Si, Ge and SiGe in the source). The novel hybrid DG-TFET improves the electrical performance (like ON current, subthreshold swing (SS), Ion/Ioff) by undercutting the top ultra-shallow source region and by sandwiching the thin Si channel onto it (between the source and gate). By doing so, along with the lateral tunneling junction (like in the conventional DG-TFET), an additional vertical tunneling junction on an ultra-shallow channel (normal to source gate dielectric) is created. The additional top thin Si channel confines the electric field and along with the lateral tunneling like in the conventional TFETs, it also ensures the possible vertical tunneling. The simulation shows significant improvement in the ON current, SS, and Ion/Ioff, etc. of the proposed hybrid DG-TFET compared to the conventional TFETs. Moreover, to optimize the ON state drain current, the simulation study of the proposed novel hybrid DG-TFET with different front gate/source overlapping has been also done in this paper.","PeriodicalId":293167,"journal":{"name":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/iSES52644.2021.00079","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, the simulation study and comparative analysis of the proposed novel hybrid Double-Gate Tunnel Field Effect Transistor (DG-TFET) are extensively done with different conventional TFET structures (different semiconductor materials like Si, Ge and SiGe in the source). The novel hybrid DG-TFET improves the electrical performance (like ON current, subthreshold swing (SS), Ion/Ioff) by undercutting the top ultra-shallow source region and by sandwiching the thin Si channel onto it (between the source and gate). By doing so, along with the lateral tunneling junction (like in the conventional DG-TFET), an additional vertical tunneling junction on an ultra-shallow channel (normal to source gate dielectric) is created. The additional top thin Si channel confines the electric field and along with the lateral tunneling like in the conventional TFETs, it also ensures the possible vertical tunneling. The simulation shows significant improvement in the ON current, SS, and Ion/Ioff, etc. of the proposed hybrid DG-TFET compared to the conventional TFETs. Moreover, to optimize the ON state drain current, the simulation study of the proposed novel hybrid DG-TFET with different front gate/source overlapping has been also done in this paper.