{"title":"MAUD: a dynamic single-assignment system","authors":"M. Lecouffe","doi":"10.1049/IJ-CDT.1979.0016","DOIUrl":null,"url":null,"abstract":"This paper presents MAUD, a parallel processor based on data-driven execution with dynamic behaviour at the execution level. MAUD is a dynamic single-assignment machine (`Machine d' Assignation Unique Dynamique'). Data-driven sequencing control is used for a producer-consumer model applied to one or several kinds of objects. The chosen objects are called blocks. The dynamic behaviour is characterised by the ability to create new blocks during program execution. The paper gives a functional description in which the different elements of the system are introduced. A suitable architecture is then proposed, based on a novel type of memory realisable with l.s.i. circuit technology.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iee Journal on Computers and Digital Techniques","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/IJ-CDT.1979.0016","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents MAUD, a parallel processor based on data-driven execution with dynamic behaviour at the execution level. MAUD is a dynamic single-assignment machine (`Machine d' Assignation Unique Dynamique'). Data-driven sequencing control is used for a producer-consumer model applied to one or several kinds of objects. The chosen objects are called blocks. The dynamic behaviour is characterised by the ability to create new blocks during program execution. The paper gives a functional description in which the different elements of the system are introduced. A suitable architecture is then proposed, based on a novel type of memory realisable with l.s.i. circuit technology.