Two cache lines prediction for a wide-issue micro-architecture

Abstract

Modern micro-architectures employ superscalar techniques to enhance system performance. The superscalar microprocessors must fetch at least one instruction cache line at a time to support high issue rate and large amount speculative executions. In this paper, we propose the Grouped Branch Prediction (GBP) that can recognize and predict multiple branches in the same instruction cache line for a wide-issue micro-architecture. Several configurations of the GBP with different group sizes are simulated. The simulation results show that the branch penalty of the group size 4 with 2048-entry is under 0.65 clock cycle. In our design, we choose the two-group scheme with group size 4. This feature achieves an average of 4.9 IPC f (the number of instructions fetched per cycle for a machine front-end). Furthermore, we extend the GBP to achieve two cache lines predictions with two fetch units. The scheme of the 2048-entry 2-group with group size 4 can produce an average of 8.4 IPC f. The performance is approximately 66.5% better than the original 2-group GBPs. The added hardware cost (41.5 k bits) is less than 40%.